PIC16LC711-04/SS【PDF 49/177 页】IC MCU OTP 1KX14 A/D 20SSOP

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Sheet目录3855

45页 46页 47页 48页 [49页]50页 51页 52页 53页

142

7593L–AVR–09/12

AT90USB64/128

15.10.12 OCR3AH and OCR3AL – Output Compare Register 3 A

15.10.13 OCR3BH and OCR3BL – Output Compare Register 3 B

15.10.14 OCR3CH and OCR3CL – Output Compare Register 3 C

The Output Compare Registers contain a 16-bit value that is continuously compared with the

counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OCnx pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are

written simultaneously when the CPU writes to these registers, the access is performed using an

8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other

16-bit registers. See “Accessing 16-bit registers” on page 117.

15.10.15 ICR1H and ICR1L – Input Capture Register 1

15.10.16 ICR3H and ICR3L – Input Capture Register 3

The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the

ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture

can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read

simultaneously when the CPU accesses these registers, the access is performed using an 8-bit

temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit

registers. See “Accessing 16-bit registers” on page 117.

Bit

OCR3A[15:8]

OCR3AH

OCR3A[7:0]

OCR3AL

Read/write

R/W

Initial value

Bit

OCR3B[15:8]

OCR3BH

OCR3B[7:0]

OCR3BL

Read/write

R/W

Initial value

Bit

OCR3C[15:8]

OCR3CH

OCR3C[7:0]

OCR3CL

Read/write

R/W

Initial value

Bit

ICR1[15:8]

ICR1H

ICR1[7:0]

ICR1L

Read/write

R/W

Initial value

Bit

ICR3[15:8]

ICR3H

ICR3[7:0]

ICR3L

Read/write

R/W

Initial value

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